NVIDIA’s orders are putting pressure on TSMC’s CoWoS capacity, with the core CoW process being shifted to external packaging and testing firms.

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2026-08-05

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According to a report by the STAR Market Daily, TSMC’s in-house CoWoS advanced packaging line is already operating at full capacity, driven by NVIDIA’s large‑scale AI GPU orders. To alleviate capacity constraints, TSMC plans to further outsource certain process steps, entrusting the CoW (chip‑on‑wafer) stage of the CoWoS process to leading packaging and testing firms such as ASE Technology Holding for contract manufacturing.

CoWoS is TSMC’s mainstream 2.5D advanced packaging solution and a critical manufacturing process for today’s high-performance AI accelerator chips. The entire architecture uses an interposer as a bridge, with the AI compute chip positioned at the center and multiple HBM high-bandwidth memory chips arranged around it, thereby shortening inter-chip data‑transfer distances and boosting bandwidth. The overall process is divided into two major stages: CoW and WoS. Previously, TSMC outsourced only the later-stage WoS substrate‑bonding step, while the more technically demanding CoW assembly phase was largely handled in‑house. This large‑scale outsourcing marks a shift in the company’s supply‑chain model.

Supply-chain reports indicate that NVIDIA has already secured TSMC’s CoWoS wafer capacity for 2026, amounting to 800,000–850,000 wafers, capturing more than half of the annual capacity allocation. With leading customers heavily consuming this capacity, packaging resources available for custom chips from Broadcom, AMD, and cloud‑service providers have become increasingly constrained.

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