1200V Vertical GaN-on-Si MOSFET

Shandong University and Huawei Technologies Co. Ltd in China have achieved 1200V breakdown performance in fully vertical gallium nitride (GaN) on silicon (Si) trench MOSFETs using fluorine (F) ion implantation termination (FIT) [Yuchuan Ma et al, IEEE Electron Device Letters, published online 8 July 2025].

Usually, mesa etch termination (MET) is used for electrical isolation of GaN semiconductor devices. However, this results in relatively sharp corners where electric fields tend to crowd, leading to premature breakdown. The breakdown voltage of MET-MOS fully vertical MOSFETs is around 650V.

Power GaN devices are competing with silicon carbide (SiC) transistors. While GaN has good performance at the 100–650V level, SiC tends to be commercially favored in 1200V applications. Achieving 1200V in devices on low-cost silicon substrates could tip the commercial balance towards GaN.

Figure 1: (a) Schematic of the structure of a silicon-based GaN trench MOSFET with fluorine implantation termination (FIT-MOS) and (b) cross-sectional scanning electron microscope (SEM) image (trench gate region).

The fully vertical transistors (Figure 1) were fabricated using GaN/silicon metal-organic chemical vapor deposition (MOCVD) epitaxial material with a buried p-GaN layer.

The researchers commented: “The conductive buffer layer consisting of AlGaN/AlN multilayers enables a fully vertical current path while achieving a fully vertical configuration without the need for complex substrate engineering processes.

The buffer also provides compressive stress, compensating for tensile stress in the overlying GaN layer that can accumulate during cooling after high-temperature MOCVD. This tensile stress can cause cracking without compensation. The researchers used X-ray analysis to estimate the threading dislocation density at 3.0x108/cm2. The corresponding estimate from cathodoluminescence was 1.4x108/cm2.

The gate trench was first etched. The GaN was activated by thermal annealing. The researchers also repaired gate trench dry-etch damage with tetramethylammonium hydroxide (TMAH) treatment.

F-ion implantation was performed at three energies (and doses): 240keV (4x1014), 140keV (2x1014), and 80keV (1.2×1014/cm2), respectively.

Atomic layer deposition (ALD) silicon dioxide (SiO2) was used as the gate dielectric. Source contact windows were opened by reactive ion etch. The source and gate metals were both chromium/gold. The drain contact consisted of the low-resistivity silicon substrate. The researchers also fabricated a device using a conventional MET process for comparison.

The FIT-MOS had a positive threshold voltage (VTH) of 3.3V. The on/off current ratio was 10 order 7. The on-current density was 8kA/cm2. The specific on-resistance (Ron,sp) was 5.6mΩ-cm2, which was described as “relatively low”.

The breakdown voltage (BV) was 1277V, compared with 567V for the comparison MET-MOS (Figure 2). The team commented: “The FIT-MOS exhibits a larger off-state current density at low VDS than the MET-MOS due to the additional vertical leakage path associated with the FIT structure.”

Figure 2: Off-state breakdown current-voltage (I–V) characteristics at 0V gate potential (VGS) of fabricated fully vertical FIT- and MET-MOS. Inset: potential leakage paths of FIT and MET-MOS.

The researchers also believe that F ions can negatively affect thermal stability by diffusing through Ga vacancies, subsequently escaping from the transistor material. The team wrote: “Adopting an optimized post-implantation annealing process can effectively reduce the off-state leakage current density and improve the thermal reliability of the FIT-MOS.”

The researchers' simulations showed that the FIT structure reduced electric field crowding, such as occurs at the mesa corner in MET-MOS transistors. The FIT simulations did show crowding near the gate trench. This could be improved by gate shielding.

Figure 3: (a) Benchmark of Ron,sp versus BV, and (b) drift layer thickness (Tdrift) versus BV, for fully vertical FIT-MOS of previously reported GaN vertical trench MOSFETs on silicon, sapphire (Sap), and GaN substrates.

The researchers also compared the Ron,sp, BV, and drift layer thickness (Tdrift) performance of their FIT devices relative to previously reported vertical GaN transistors (Figure 3). Combining breakdown and on-resistance, the BV2/Ron,sp Baliga figure of merit (BFOM) gave a value of 291MW/cm2, comparable to the value for devices fabricated on more expensive native GaN substrates. At the same time, the FIT-MOS had a thinner drift layer with similar BV performance compared to such expensive GaN/GaN transistors (7μm, while 1200V BV exceeds 10μm).