Process Technology

Jan 21,2026

As the feature size of integrated circuits continues to shrink, the impact of chemical-mechanical polishing and subsequent cleaning processes in the back-end-of-line copper interconnect manufacturing on device performance and long-term reliability is becoming increasingly prominent.

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Jan 19,2026

The variation pattern of the selectivity ratio between SiO₂ and Si₃N₄ in BOE buffer solution at different temperatures.

BOE buffer solution, with its controllable etching rate and excellent material selectivity, is commonly used in integrated circuit manufacturing for patterning and removing SiO2 layers.

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The variation pattern of the selectivity ratio between SiO₂ and Si₃N₄ in BOE buffer solution at different temperatures.

Jan 15,2026

Post-etch cleaning

As the feature sizes of integrated circuits continue to shrink and three-dimensional structures become increasingly widespread, the importance of post-etch cleaning processes has grown significantly. Residues generated during etching not only affect the electrical performance of devices but can also lead to failures in subsequent process steps.

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Jan 09,2026

The Fundamentals and Reaction Mechanism of Wet Cleaning

In the semiconductor manufacturing process, contaminants on the wafer surface—including particles, organic substances, metal ions, and natural oxide films—can severely compromise device performance and reliability. Wet cleaning, which uses chemical solutions to regulate surface conditions at the nanoscale, not only removes these contaminants but also provides an ideal “starting point” for subsequent process steps such as thin-film deposition, photolithography, and etching.

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The Fundamentals and Reaction Mechanism of Wet Cleaning

Jan 07,2026

Temperature Control of SC-1 and SC-2 Solutions at Different Process Nodes

In semiconductor manufacturing, SC-1 (Standard Clean-1, an ammonia-hydrogen peroxide mixture) and SC-2 (Standard Clean-2, a hydrochloric acid-hydrogen peroxide mixture) are critical wet-etching cleaning processes. Temperature control for these processes must be finely optimized based on the process node, the type of contaminants, and the characteristics of the thin films, in order to ensure effective cleaning while minimizing damage to the device structure.

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Temperature Control of SC-1 and SC-2 Solutions at Different Process Nodes

Dec 29,2025

Mechanism of High-Temperature SPM Cleaning for Removing Contaminants from Nickel Surfaces

Wet chemical cleaning is one of the key technologies for removing surface contamination. Among these, the SPM solution—a mixture of sulfuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂)—has emerged as an efficient cleaning agent thanks to its powerful oxidizing and dissolving capabilities. Particularly under high-temperature conditions, the reaction kinetics of the SPM solution are significantly enhanced, enabling it to effectively remove a wide variety of contaminants from nickel surfaces.

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Mechanism of High-Temperature SPM Cleaning for Removing Contaminants from Nickel Surfaces

Dec 23,2025

Cavitation effect of ultrasound

The cavitation effect of ultrasound is a unique physical phenomenon triggered when ultrasonic waves propagate through a medium. At its core, it involves the generation, growth, and collapse of tiny bubbles (cavitation bubbles) within the medium.

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Dec 17,2025

Technical Advantages of Fully Automatic Wet Etching and Cleaning Machines

The fully automatic wet etching and cleaning machine is an automated system specifically designed for surface treatment and cleaning of semiconductor wafers, electronic components, and microstructured devices.

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Technical Advantages of Fully Automatic Wet Etching and Cleaning Machines

Dec 12,2025

Wet-etching equipment cleaning solution

In the semiconductor manufacturing process, the cleanliness of the wafer surface directly affects device performance and yield. As a critical surface treatment process, wet cleaning hinges on the selection and formulation of chemical solutions.

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Dec 10,2025

Marangoni drying process parameters

As semiconductor process nodes shrink below 28 nm, traditional drying technologies can no longer meet the requirements for protecting high aspect-ratio structures and controlling nanoscale residues.

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